In U.S. Pat. No. 4,085,644 there is described a Polyphonic Tone Synthesizer in which a master data set is computed and stored in a main register from which it is transferred to note registers of a plurality of tone generators. The master data set defines the amplitudes of equally spaced points along a half cycle of the audio waveform of the musical tones being generated. Each tone generator receives the words in the master data set and applies them to a digital-to-analog converter at a rate determined by the fundamental pitch of the respective tones being generated by the Polyphonic Tone Synthesizer.
One of the features of the Polyphonic Tone Synthesizer, as described in the above-identified patent, is that the transfer of successive words from the master data set in the main register to an individual note register in the respective tone generators is synchronized with the transfer of words from the note register to the digital-to-analog converter in the respective tone generators. This feature permits the master data set defining the waveform to be recomputed and loaded in the respective tone generators without interrupting the generation of the respective musical notes by the tone generators, thus permitting the waveform of a musical tone to be changed with time without interrupting the resulting musical tone.
The rate at which the waveform can be varied as a function of time is limited by the length of time for a computation cycle during which the master data set is generated and the length of time required to transfer the data from the main register to the note registers in each of the tone generators. Methods for reducing the length of the transfer are described in the copending application Ser. No. 10,946 filed Feb. 9, 1979 entitled "Data Transfer Apparatus For Digital Polyphonic Tone Synthesizer." The referenced application and the present application have a common assignee.
An obvious method of reducing the time required for the computation cycle is to simply increase the frequency of the logic master clock which provides the timing signals for the system logic. There are practical as well as economic limitations imposed upon the speed, or frequency, of the master clock. If the Polyphonic Tone Synthesizer is implemented with microelectronics, then the present state-of-the-art limits the master clock to about 2 to 3 Mhz. Since the cost of microelectronics rises very fast with the high end of the speed limits, it is desirable to achieve a decreased computation cycle time without increasing the speed of the master clock.
In U.S. Pat. No. 4,085,644 a procedure was described for reducing the length of the computation cycle by one-half the time by computing 32 data words rather than the full set of 64 words used to define a master data set corresponding to a waveshape having a maximum of 32 harmonics. This reduction of one-half in the number of data points required by the master data set is accomplished by generating the master data having a prespecified symmetry of data points. The symmetry is obtained by using either only sine (or odd symmetric orthogonal functions) terms or only cosine (or even symmetric orthogonal functions) in the calculation of the master data set. The second 32 data words required by the note registers is obtained by reading the data from the main register forward and backward. In the backward read mode a 2's complement operation is applied to the addressed master data set words if the sine terms, or odd symmetric, calculations were used to generate the master data set. No change in the addressed master data set is required if the cosine terms, or even symmetric, calculations were used to generate the master data set.